Some conventional SiC JFETs are constructed from two different epitaxial layers grown on a semiconductor substrate in order to adequately form all implanted regions of the device, i.e. the drain, source, gate, and an integrated body diode. For example, the drain is implanted in the substrate, the body diode, source and buried gate are implanted in a first (lower) epitaxial layer, and the top gate is implanted in a second (upper) epitaxial layer. Alignment marks on the first epitaxial layer are severely degraded during growth of the second epitaxial layer and, therefore, the alignment of the top gate to the buried gate is complex and inaccurate. This in turn limits the pitch scaling, i.e. size reduction of the device.
In addition, a significant pinch-off voltage variation occurs due to a thickness variation of the second epitaxial layer. A very complex process is needed to switch off a SiC JFET with a poorly controlled pinch-off voltage, and the use of such devices in parallel configuration (e.g. in a module application) is nearly impossible or at least quite complex.
Furthermore, a significant number of photolithography steps are needed to form the different implanted regions of a conventional SiC JFET with two epitaxial layers. Other conventional SiC JFETs are constructed from a single epitaxial layer grown on a semiconductor substrate, but do not include an integrated body diode. A body diode enables a JFET to conduct current in both directions. Body diodes are widely used as freewheeling diodes for inductive loads in configurations such as H-bridge or half bridge. SiC body diodes usually have high forward voltage drop, but can handle large currents and are sufficient in many applications, reducing part count and, thus, device cost and board space.